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| 1 ps8410 08/11/99 ref/sel2 1 v dd3.3 2 xtal_in 3 3.3v 2.5v 2.5v 3.3v 3.3v 3.3v xtal_out 4 v ss3.3 5 v ss3.3 6 3v66 0 7 3v66 1 8 v dd3.3 9 v dd3.3 10 pci 0 11 pci 1 12 pci 2 13 v ss3.3 14 pci 3 15 pci 4 16 v ss3.3 17 pci 5 18 pci 6 19 pci 7 20 v dd3.3 21 v dda 22 v ssa 23 v ss3.3 24 48mhz0 25 48mhz1 26 v dd3.3 27 sel0 28 v ss2.5 apic0 apic1 v dd2.5 cpu 0 v dd2.5 cpu 1 cpu 2 v ss2.5 56 v ss3.3 55 sdram0 54 sdram1 53 v dd3.3 52 sdram2 51 sdram3 50 v ss3.3 49 sdram4 48 sdram5 47 v dd3.3 46 sdram6 45 sdram7 44 v ss3.3 43 dclk 42 v dd3.3 41 40 39 38 37 36 35 34 33 pwr_dwn# sclk sdata sel1 32 31 30 29 3.3v 56-pin (v56) dclk ref osc ref x in x out 48 mhz 0-1 3v66 0-1 pci 0-7 sdram 0-7 cpu 0-2 pll2 pll1 2 2 apic 0-1 2 3 8 8 pin configuration 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c110e clock solution for 133 mhz celeron/pentium ii/iii processors block diagram features ? 3 of 2.5v 66/100/133 mhz cpu (cpu[0-2]) ? 2 of 2.5v 33 mhz apic (apic[0-1]) ? 9 of 3.3v 100/133 mhz sdram (sdram[0-7], dclk) ? 8 of 3.3v 33 mhz pci (pci[0-7]) ? 2 of 3.3v 66 mhz (3v66 [0-1]) ? 2 of 3.3v 48 mhz (48mhz [0-1]) ? 1 of 3.3v 14.3 mhz (ref) ? selectable cpu and sdram clocks (on power up only) ? power down function using pwr_dwn# ? spread spectrum enable/disable by i 2 c ?i 2 c interface to turn off unused clocks ? 56 pin ssop package (v) description pericom pi6c110e integrates a dual pll clock generator, sdram buffer and i 2 c interface. the clock generator section comprised of an oscillator, 2 low jitter phased locked loop, skew control, and power down logic. the sdram buffers are high speed and low skew to handle data transfers in excess of 133 mhz. when spread spectrum mode is enabled, all clock outputs are modulated except for ref and 48 mhz[0-1] outputs. these clocks are down spread linearly (triangular modulation) by +0%, ?0.6%. to minimize power consumption and emi radiation some unused outputs can be turned off. two wire i 2 c interface is used to enable/ disable spread spectrum mode, and to turned off pci clocks, cpu clocks, and 48 mhz clocks. for low power sleep mode, the entire device can be placed to power down mode. driving the pwr_dwn# to low state disables the entire chip. in this state the crystal oscillator, and both plls are turned off. furthermore, all outputs are deactivated to low state, all inputs are inactive except for pwr_dwn#. all trademarks are of their respective companies. v
2 ps8410 08/11/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c110e clock solution for 133 mhz celeron/pentium ii/iii processors n i pe p y t. y t qs / pl o b m y sn o i t p i r c s e d 1o / i13 . 32 l e s / f e r s i n i p s i h t p u r e w o p g n i r u d . t u p t u o e c n e r e f e r z h m 8 1 3 . 4 1 y l l a m r o n . m h o k 0 0 1 / w n w o d d e l l u p y l l a n r e t n i . 2 t i b k c o l c , 2 l e s s a d e l p m a s 3i13 . 3n i _ l a t xt u p n i l a t s y r c z h m 8 1 3 . 4 1 4o13 . 3t u o _ l a t xt u p t u o l a t s y r c z h m 8 1 3 . 4 1 8 , 7o23 . 3] 1 - 0 [ 6 6 v 3z h m 6 6 , 5 1 , 3 1 , 2 1 , 1 1 0 2 , 9 1 , 8 1 , 6 1 o8 3 . 3] 7 - 0 [ i c ps t u p t u o i c p 6 2 , 5 2o13 . 3] 1 - 0 [ z h m 8 4t u p t u o z h m 8 4 9 2 , 8 2i23 . 3] 1 - 0 [ l e sp u l l u p l a n r e t n i , s t u p n i t c e l e s y c n e u q e r f l e v e l l t t v l 0 3o / i13 . 3a t a d si 2 p u l l u p l a n r e t n i , a t a d s e l b i t a p m o c c 1 3i13 . 3k c o l c si 2 p u l l u p l a n r e t n i , k c o l c s e l b i t a p m o c c 2 3i13 . 3# n w d r w pw o l e v i t c a , t u p n i l o r t n o c n w o d r e w o p l e v e l l t t v l , 9 3 , 7 3 , 6 3 , 4 3 6 4 , 5 4 , 3 4 , 2 4 , 0 4 o9 3 . 3 , k l c d ] 7 - 0 [ m a r d s . ] 2 - 0 [ l e s n o g n i d n e p e d z h m 3 3 1 / 0 0 1 . s t u p t u o k l c d d n a m a r d s i h g u o r h t f f o d e n r u t e b n a c ] 7 - 0 [ m a r d s 2 . k l c d t o n t u b , c 2 5 , 0 5 , 9 4o35 . 2] 2 - 0 [ u p c] 2 - 0 [ l e s n o g n i d n e p e d z h m 3 3 1 / 0 0 1 / 6 6 . t u p t u o k c o l c s u b t s o h 5 5 , 4 5o25 . 2] 1 - 0 [ c i p ak c o l c i c p o t s u o n o r h c n y s , k c o l c c i p a z h m 3 3 , 7 2 , 1 2 , 0 1 , 9 , 2 4 4 , 8 3 , 3 3 r w p83 . 3v 3 . 3 d d y l p p u s r e w o p v 3 . 3 , 4 2 , 7 1 , 4 1 , 6 , 5 7 4 , 1 4 , 5 3 d n g8a / nv 3 . 3 s s d n u o r g v 3 . 3 3 5 , 1 5r w p25 . 2v 5 . 2 d d y l p p u s r e w o p v 5 . 2 6 5 , 8 4d n g2a / nv 5 . 2 s s d n u o r g v 5 . 2 2 2r w p13 . 3v a d d y l p p u s r e w o p e r o c v 3 . 3 3 2d n g1a / nv a s s d n u o r g e r o c v 3 . 3 pin description table 2 l e s1 l e s0 l e sn o i t c n u f x0 0 e t a t s - i r t x0 1 t s e t 010 z h m 0 0 1 = m a r d s , z h m 6 6 = u p c 011 z h m 0 0 1 = m a r d s , z h m 0 0 1 = u p c 110 z h m 3 3 1 = m a r d s , z h m 3 3 1 = u p c 111 z h m 0 0 1 = m a r d s , z h m 3 3 1 = u p c frequency select function table 3 ps8410 08/11/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c110e clock solution for 133 mhz celeron/pentium ii/iii processors symbol parameter min. max. units notes v ih3 3.3v input high voltage -0.5 4.6 v 1 v il3 3.3v input low voltage -0.5 v esd prot. input esd protection 2000 v 2 dc specifications dc parameters must be sustainable under steady state (dc) conditions. notes: 1. maximum v ih is not to exceed maximum v dd . 2. human body model. symbol parameter min. max. units notes v dda 3.3v core supply voltage -0.5 4.6 v v dd2.5 2.5v i/o supply voltage -0.5 3.6 v v dd3.3 3.3v i/o supply voltage -0.5 4.6 v t s storage temperature -65 150 c absolute maximum dc power supply absolute maximum dc i/o symbol parameter condition min. max. units notes v dda 3.3v core supply voltage 3.3v 5% 3.135 3.465 v 2 v dd3.3 3.3v i/o supply voltage 3.3v 5% 3.135 3.465 v 2 v dd2.5 2.5v i/o supply voltage 2.5v 5% 2.375 2.625 v 2 v ih3 3.3v input high voltage v dda 2.0 v dd +0.3 v 4 v il3 3.3v input low voltage v ss -0.3 0.8 v 4 i il input leakage current 0 5 ps8410 08/11/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c110e clock solution for 133 mhz celeron/pentium ii/iii processors ac timing specifications (see notes on next page) l o b m y sr e t e m a r a p z h m 6 6z h m 0 0 1z h m 3 3 1 s t i n us e t o n . n i m. x a m. n i m. x a m. n i m. x a m d o i r e p td o i r e p k l c u p c / t s o h0 . 5 15 . 5 10 . 0 15 . 0 15 . 70 . 8s n7 , 2 h g i h te m i t h g i h k l c u p c / t s o h2 . 5a / n0 . 3a / n7 8 . 1a / ns n3 w o l te m i t w o l k l c u p c / t s o h0 . 5a / n8 . 2a / n7 6 . 1a / ns n4 e t a r e g d e) v 5 . 2 r e f f u b 1 e p y t ( e t a r e g d e g n i s i r0 . 10 . 40 . 10 . 40 . 10 . 4s n / v e t a r e g d e) v 5 . 2 r e f f u b 1 e p y t ( e t a r e g d e g n i l l a f0 . 10 . 40 . 10 . 40 . 10 . 4s n / v e s i r te m i t e s i r k l c u p c / t s o h4 . 06 . 14 . 06 . 14 . 06 . 1s n6 , 1 l l a f te m i t l l a f k l c u p c / t s o h4 . 06 . 14 . 06 . 14 . 06 . 1s n6 , 1 d o i r e p t d o i r e p k l c z h m 3 3 c i p a 0 . 0 3 a / n 0 . 0 3 a / n 0 . 0 3 a / n s n 7 , 2 h g i h t e m i t h g i h k l c z h m 3 3 c i p a 0 . 2 1 a / n 0 . 2 1 a / n 0 . 2 1 a / n s n 3 w o l t e m i t w o l k l c z h m 3 3 c i p a 0 . 2 1 a / n 0 . 2 1 a / n 0 . 2 1 a / n s n 4 e t a r e g d e ) v 5 . 2 r e f f u b 1 e p y t ( e t a r e g d e g n i s i r 0 . 1 0 . 4 0 . 1 0 . 4 0 . 1 0 . 4 s n / v e t a r e g d e ) v 5 . 2 r e f f u b 1 e p y t ( e t a r e g d e g n i l l a f 0 . 1 0 . 4 0 . 1 0 . 4 0 . 1 0 . 4 s n / v e s i r t e m i t e s i r k l c z h m 3 3 c i p a 4 . 0 6 . 1 4 . 0 6 . 1 4 . 0 6 . 1 s n 6 , 1 l l a f t e m i t l l a f k l c z h m 3 3 c i p a 4 . 0 6 . 1 4 . 0 6 . 1 4 . 0 6 . 1 s n 6 , 1 d o i r e p td o i r e p k l c 6 6 v 30 . 5 10 . 6 10 . 5 10 . 6 10 . 5 10 . 6 1s n7 , 2 h g i h te m i t h g i h k l c 6 6 v 35 2 . 5a / n5 2 . 5a / n5 2 . 5a / ns n3 w o l te m i t w o l k l c 6 6 v 35 . 5a / n5 . 5a / n5 . 5a / ns n4 e t a r e g d e) v 3 . 3 r e f f u b 5 e p y t ( e t a r e g d e g n i s i r0 . 10 . 40 . 10 . 40 . 10 . 4s n / v e t a r e g d e) v 3 . 3 r e f f u b 5 e p y t ( e t a r e g d e g n i l l a f0 . 10 . 40 . 10 . 40 . 10 . 4s n / v e s i r te m i t e s i r k l c 6 6 v 35 . 00 . 25 . 00 . 25 . 00 . 2s n6 , 1 l l a f te m i t l l a f k l c 6 6 v 35 . 00 . 25 . 00 . 25 . 00 . 2s n6 , 1 d o i r e p t d o i r e p k l c c i p a & i c p 0 . 0 3 a / n 0 . 0 3 a / n 0 . 0 3 a / n s n 7 , 2 h g i h t e m i t h g i h k l c c i p a & i c p 0 . 2 1 a / n 0 . 2 1 a / n 0 . 2 1 a / n s n 3 w o l t e m i t w o l k l c c i p a & i c p 0 . 2 1 a / n 0 . 2 1 a / n 0 . 2 1 a / n s n 4 e t a r e g d e ) v 3 . 3 r e f f u b 5 e p y t ( e t a r e g d e g n i s i r 0 . 1 0 . 4 0 . 1 0 . 4 0 . 1 0 . 4 s n / v e t a r e g d e ) v 3 . 3 r e f f u b 5 e p y t ( e t a r e g d e g n i l l a f 0 . 1 0 . 4 0 . 1 0 . 4 0 . 1 0 . 4 s n / v e s i r t e m i t e s i r k l c c i p a & i c p 5 . 0 0 . 2 5 . 0 0 . 2 5 . 0 0 . 2 s n 6 , 1 l l a f t e m i t l l a f k l c c i p a & i c p 5 . 0 0 . 2 5 . 0 0 . 2 5 . 0 0 . 2 s n 6 , 1 d o i r e p td o i r e p k l c m a r d sa / na / n5 . 0 15 . 0 15 . 70 . 8s n7 , 2 h g i h te m i t h g i h k l c m a r d sa / na / n0 . 3a / n7 8 . 1a / ns n3 w o l te m i t w o l k l c m a r d sa / na / n8 . 2a / n7 6 . 1a / ns n4 e t a r e g d e) v 3 . 3 r e f f u b 4 e p y t ( e t a r e g d e g n i s i ra / na / n5 . 10 . 40 . 10 . 4s n / v e t a r e g d e) v 3 . 3 r e f f u b 4 e p y t ( e t a r e g d e g n i l l a fa / na / n5 . 10 . 40 . 10 . 4s n / v e s i r te m i t e s i r k l c m a r d sa / na / n4 . 06 . 14 . 06 . 1s n6 , 1 l l a f te m i t l l a f k l c m a r d sa / na / n4 . 06 . 14 . 06 . 1s n6 , 1 h z p t , l z p t ) s t u p t u o l l a ( y a l e d e l b a n e t u p t u o 0 . 1 0 . 0 1 0 . 1 0 . 0 1 0 . 1 0 . 0 1 s n h z p t , z l p t ) s t u p t u o l l a ( y a l e d e l b a s i d t u p t u o 0 . 1 0 . 0 1 0 . 1 0 . 0 1 0 . 1 0 . 0 1 s n e l b a t s t p u - r e w o p m o r f n o i t a z i l i b a t s k c o l c l l a 3 3 3 s m 5 6 ps8410 08/11/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c110e clock solution for 133 mhz celeron/pentium ii/iii processors ac timing notes: 1. output drivers must have monotonic rise/fall times through the specified v ol /v oh levels. 2. period, jitter, offset and skew measured on rising edge @1.25v for 2.5v clocks and @ 1.5v for 3.3v clocks. 3. t high is measured at 2.0v for 2.5v outputs, 2.4v for 3.3v outputs. 4. t low is measured at 0.4v for all outputs. 5. the time specified is measured from when the power supply achieves its nominal operating level (typical condition v dd3.3v = 3.3v) until the frequency output is stable and operating within specification. 6. t rise and t fall are measured as a transition through the threshold region v ol = 0.4v and v oh = 2.0v (1ma) jedec specification. 7. the average period over any 1 m s period of time must be greater than the minimum specified period. pin-pin output skew cycle-cycle skew, jitter g roup max. jitter duty cycle nom v dd measure point cpu 175ps 250ps 45/55 2.5v 1.25v sdram 250ps 250ps 45/55 3.3v 1.5v apic 250ps 500ps 45/55 2.5v 1.25v 48 mhz n/a 500ps 45/55 3.3v 1.5v 3v66 175ps 500ps 45/55 3.3v 1.5v pci 500ps 500ps 45/55 3.3v 1.5v ref n/a 1000ps 45/55 3.3v 1.5v group skew and jitter limits clock output wave trise 2.0 0.4 tperiod 1.25 thigh tlow duty cycle 2 .5v clocking interface o u t pu t buffer test point test load tfall trise 2.4 0.4 tperiod 1.5 thigh tlow duty cycle 3.3v clocking interface tfall 2 output output waveform figure 1. 7 ps8410 08/11/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c110e clock solution for 133 mhz celeron/pentium ii/iii processors vol = 0.4v vih = 1.7v 1.25v vi l = 0.7 v voh = 2.0v measurement points for component output measurement points for system level inputs v dd 2.5 vs s vol = 0.4v vih = 2.0v 1.5v vi l = 0.8 v voh = 2.4v measurement points for component output measurement points for system level inputs v dd 2.5 vs s 2.5 volt measure points 3.3 volt measure points figure 2. component versus system measure points note : only offset specifications listed above are guaranteed/tested. the specification is treated as any output within first specified bank to any output of the second specified bank. pin-pin skew is implied within offset specification, jitter is not. previous offset specifications such as cpu to pci offset are no longer required. group to group skew tolerance p u o r g 6 6 u p c6 6 u p c0 0 1 u p c0 0 1 u p c3 3 1 u p c3 3 1 u p c t e s f f oe c n a r e l o tt e s f f oe c n a r e l o tt e s f f oe c n a r e l o t 0 0 1 m a r d s o t u p cs n 5 . 2s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5 3 3 1 m a r d s o t u p ca / na / na / na / ns n 0 . 5s p 0 0 5 6 6 v 3 o t u p cs n 0 . 5s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5 6 6 v 3 o t 0 0 1 m a r d ss n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5 6 6 v 3 o t 3 3 1 m a r d sa / na / na / na / ns n 0 . 0s p 0 0 5 i c p o t 6 6 v 3s n 5 . 3 ~ 5 . 1s p 0 0 5s n 5 . 3 ~ 5 . 1s p 0 0 5s n 5 . 3 ~ 5 . 1s p 0 0 5 c i p a o t i c ps n 0 . 0s n 0 . 1s n 0 . 0s n 0 . 1s n 0 . 0s n 0 . 1 t o d & z h m 8 4c n y s aa / nc n y s aa / nc n y s aa / n 8 ps8410 08/11/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c110e clock solution for 133 mhz celeron/pentium ii/iii processors group offset measurement clarification 0.0ns 10.0ns 20.0ns 30.0ns 7.5ns 7.5ns 5.0ns 5.0ns 0.0ns 0.0ns 0.0ns 0.0ns 7.5ns 0.0ns 3.75ns 1.5~3.5ns 0.0ns 15ns 22.5ns cpu66 sdram100 3v66 cpu100 sdram100 3v66 cpu133 sdram100 3v66 cpu133 sdram133 3v66 3v66 pci apic 9 ps8410 08/11/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c110e clock solution for 133 mhz celeron/pentium ii/iii processors truth table notes: 1. required for board level ?bed of nails? testing. 2. ?normal? mode of operation. 3. tclk is a test clock over driven on the xtal_in input during test mode. 4. required for dc output impedance verification. 5. range of reference frequency allowed is min = 14.316 mhz, nominal = 14.31818 mhz, max = 14.32 mhz. 6. frequency accuracy of 48 mhz is 167ppm to match 48 mhz default. 2 l e s1 l e s0 l e su p cm a r d s6 6 v 3i c pz h m 8 4f e rc i p as e t o n x00 z - i hz - i hz - i hz - i hz - i hz - i hz - i h1 x01 2 / k l c t2 / k l c t3 / k l c t6 / k l c t2 / k l c tk l c t6 / k l c t4 , 3 010 z h m 6 6z h m 0 0 1z h m 6 6z h m 3 3z h m 8 4z h m 8 1 3 . 4 1z h m 3 3 6 , 5 , 2 011 z h m 0 0 1z h m 0 0 1z h m 6 6z h m 3 3z h m 8 4z h m 8 1 3 . 4 1z h m 3 3 110 z h m 3 3 1z h m 3 3 1z h m 6 6z h m 3 3z h m 8 4z h m 8 1 3 . 4 1z h m 3 3 111 z h m 3 3 1z h m 0 0 1z h m 6 6z h m 3 3z h m 8 4z h m 8 1 3 . 4 1z h m 3 3 clock enable configuration notes: 1. low means outputs held static low. 2. on means active. 3. pwr_dwn# pulled low, impacts all outputs including ref and 48 mhz outputs. # n w d _ r w pu p cm a r d sc i p a6 6 v 3i c p , f e r z h m 8 4 c s os o c v 0w o lw o lw o lw o lw o lw o lf f of f o 1n on on on on on on on o system clock design considerations pi6c110e supports 4 operational modes. it varies the fsb (front side bus) and sdram clock frequencies. fsb selection is 66 mhz, 100 mhz or 133 mhz. sdram frequency is either 100 mhz or 133 mhz. the supported modes are: sel[2:0] mode cpu sdram 3v66 apic/pci 0 1 0 mode 0 66 100 66 33 0 1 1 mode 1 100 100 66 33 default 1 1 0 mode 2 133 133 66 33 1 1 1 mode 3 133 100 66 33 the clock select pins, sel[2:0] have the appropriate 100k (20k) internal pull up and pull down to allow the system defaults to 100 mhz cpu clock and 100 mhz sdram clock without external strapping resistor. sel2 in pulled down, sel1 and sel0 is pulled up to indi cate ?0 1 1?. the apic clock is a 33 mhz, the same frequency and phase as the pci clocks, except it is powered by 2.5v supply. apic and pci clocks are always in phase with the other clocks. in mode 0, cpu and 3v66 are inverted. in mode 1 and mode 3, cpu and sdram clocks are inverted. system debug and timing margin analysis to support system debug and to measure/test margin analysis, the internal pi6c110e oscillator circuits allows the input crysta l frequency to be driven with parallel resonant crystal with frequency range of 10 mhz to 20 mhz in laboratory environment. the alternativ e is to put the device in test mode, sel2 = ?don?t care?, sel1 = ?1? and sel0 = ?0?. then drive a clock signal to xtal_in (pin 3) from a signal generator and float xtal_out (pin 4). 10 ps8410 08/11/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c110e clock solution for 133 mhz celeron/pentium ii/iii processors power management notes: 1. clock on/off latency is defined in the number of rising edges of free running pci clock between the clock disable goes low/high to the first valid clock comes out of the device. 2. power up latency is when pwrdwn# goes inactive (high) to when the first valid clocks are driven from the device. the power down selection is used to put the part into a very low power state without turning off the power to the part. pwrdwn# is an asynchronous active low input. this signal is synchronized internal to the device prior to powering down the clock synthesizer. pwrdwn# is an asynchronous function for powering up the system. internal clocks are not running after the device is put in power down. when pwrdwn# is active low all clocks are driven l a n g i se t a t s l a n g i s y c n e t a l s k c o l c i c p f o s e g d e g n i s i r f o . o n # n w d r w p) n o i t a r e p o l a m r o n ( 1s m 3 ) n w o d r e w o p ( 0w o l e b m a r g a i d g n i m i t e e s power management maximum current n o i t i d n o c , n o i t p m u s n o c y l p p u s 5 . 2 . x a m , s d a o l p a c t e e r c s i d . x a m v 5 . 2 d d v 5 2 6 . 2 = v = s t u p n i c i t a t s l l a 3 . 3 d d v r o s s , n o i t p m u s n o c y l p p u s 3 . 3 . x a m , s d a o l p a c t e e r c s i d . x a m v 3 . 3 d d , v 5 6 4 . 3 = v = s t u p n i c i t a t s l l a 3 . 3 d d v r o s s e d o m n w o d r e w o p ) 0 = ) # n w d r w p ( a 0 0 1a 0 0 2 z h m 0 0 1 = m a r d s , z h m 6 6 = u p c 0 1 0 = ] 2 - 0 [ l e s a m 0 7a m 0 8 2 z h m 0 0 1 = m a r d s , z h m 0 0 1 = u p c 1 1 0 = ] 0 - 2 [ l e s a m 0 0 1a m 0 8 2 z h m 3 3 1 = m a r d s , z h m 3 3 1 = u p c 0 1 1 = ] 0 - 2 [ l e s d b td b t z h m 0 0 1 = m a r d s , z h m 3 3 1 = u p c 1 1 1 = ] 0 - 2 [ l e s d b td b t to a low value and held prior to turning off the vco?s and the crystal. the power -up latency needs to be less than 3ms. the ref and 48 mhz clocks are expected to be stopped in the low state as soon as possible. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. 11 ps8410 08/11/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c110e clock solution for 133 mhz celeron/pentium ii/iii processors pwrdwn# timing diagram notes: 1. once the pwrdwn# signal is sampled low for two consecutive rising edges of cpu clock, clocks of interest should be held low o n the next high to low transition. 2. pwrdwn# is an asynchronous input and metastable conditions could exist. this signal is synchronized inside the part. 3. the shaded sections on the sdram, ref, and 48 mhz clocks indicate don?t care states. 4. diagrams shown with respect to 100 mhz. similar operation when cpu is 66/133 mhz. vco internal cpu 3v66 pci 33 mhz apic 33mhz pwrdwn# sdram ref 14.318 mhz 48 mhz 25ns 50ns 75ns center 0ns 12 minimum and maximum lumped capacitive loads k c o l c . n i m d a o l . x a m d a o l s t i n us e t o n u p c0 10 2 f p s d a o l 2 e l b i s s o p , d a o l e c i v e d 1 i c p0 10 3s t n e m e r i u q e r 1 . 2 i c p t e e m t s u m m a r d s0 20 3s c e p s 3 3 1 c p / 0 0 1 c p 6 6 v 30 10 3s d a o l 2 e l b i s s o p , d a o l e c i v e d 1 z h m 8 40 10 2, d a o l e c i v e d 1 f e r0 10 2, d a o l e c i v e d 1 c i p a0 10 2, d a o l e c i v e d 1 12 ps8410 08/11/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c110e clock solution for 133 mhz celeron/pentium ii/iii processors note: the acknowledgment bit is returned by the slave/receiver (the clock driver). i 2 c considerations 1. address assignment: any clock driver in this specification can use the single, 7 bit address shown below. all devices can use the address if only one master clock driver is used in a design. the following address was confirmed by philips on 09/04/96. a6 a5 a4 a3 a2 a1 a0 r/w# 1 1 0 1 0 0 1 0 note: the r/w# bit is used by the i 2 c controller as a data direction bit. a ?zero? indicates a transmission (write) to the clock device. a ?one? indicates a request for data (read) from the clock driver. since the definition of the clock buffer only allows the co ntroller to write data; the r/w# bit of the address will always be seen as a ?zero.? 2. slave/receiver: the clock driver is assumed to require only slave/receiver functionality. 3. data transfer rate: 100 kbits/s (standard mode) is the base functionality. 4. logic levels: assume all devices are based on a 3.3 volt supply. 5. data byte format: byte format is 8-bits. 6. data protocol: to simplify the clock i 2 c interface, the clock driver serial protocol was specified to use only block writes from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. indexed bytes are not allowed. the clock driver must meet this protocol which is more rigorous than previously stated i 2 c protocol. treat the description from the viewpoint of controller. the controller ?writes? to the clock driver and if possible would ?read? from the clock driver. ?the block write begins with a slave address and a write condition. after the command code the host (controller) issues a byte count which describes how many more bytes will follow in the message. if the host had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. the byte count may not be 0. a block write command is allowed to transfer a maximum of 32 data bytes. 1 bit 7 bits 1 1 8 bits 1 start bit slave address r/w ack command code ack byte count = n ack data byte 1 ack data byte 2 ack ... data byte n ack stop 1 bit 8 bits 1 8 bits 1 8 bits 1 1 13 ps8410 08/11/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c110e clock solution for 133 mhz celeron/pentium ii/iii processors consider the command code and the byte count bytes required as the first two bytes of any transfer. the command code is softwa re programmable via the controller, but will be specified as 0000 0000 in the clock specification. the byte count byte is the num ber of additional bytes required for the transfer, not counting the command code and byte count bytes. additionally, the byte count b yte is required to be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement. for example: 7. clock stretching: the clock device must not hold/stretch the sclk or sdata lines low for more than 10 ms. clock stretching is discouraged and should only be used as a last resort. stretching the clock/data lines for longer than this time puts the devi ce in an error/ time-out mode and may not be supported in all platforms. it is assumed that all data transfers can be completed as specified w ithout the use of clock/data stretching. 8. general call: it is assumed that the clock driver will not have to respond to the ?general call.? 9. electrical characteristics: all electrical characteristics must meet the standard mode specifications found in section 15 of the i 2 c specification. a) pull-up resistors: there is a 100k internal resistor pull-ups on the sdata and sclk inputs. assume that the board designer will use a single external pull-up resistor for each line and that these values are in the 5-6k ohm range. assume one i 2 c device per dimm (serial presence detect), one i 2 c controller, one clock driver plus one/two more i 2 c devices on the platform for capacitive loading purposes. b) input glitch filters: only fast mode i 2 c devices require input glitch filters to suppress bus noise. the clock driver is specified as a standard mode device and is not required to support this feature. 10. pwrdwn#: if a clock driver is placed in power down mode, the sdata and sclk inputs are tri-stated and the device must retain all programming information. for specific i 2 c information consult the philips i 2 c peripherals data handbook ici2 (1996) a transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. the serial controller interface can be simplified by discarding the information in both the command code and the byte count bytes and simply reading all the bytes that are sent to the clock driver after being addressed by the controller. it is expected that the controller will not p rovide more bytes than the clock driver can handle. e t y b t n u o c e t y bs e t o n b s mb s l 0 0 0 00 0 0 0. e t y b e n o t s a e l t a e v a h t s u m . d e w o l l a t o n 0 0 0 01 0 0 0) c e p s n i 0 e t y b y l t n e r r u c ( r e t s i g e r t c e l e s y c n e u q e r f d n a l a n o i t c n u f r o f a t a d 0 0 0 00 1 0 0) 1 e t y b n e h t , 0 e t y b ( a t a d f o s e t y b o w t t s r i f s d a e r 0 0 0 01 1 0 0) r e d r o n i 2 , 1 , 0 e t y b ( a t a d f o s e t y b e e r h t t s r i f s d a e r 0 0 0 00 0 1 0) r e d r o n i 3 , 2 , 1 , 0 e t y b ( a t a d f o s e t y b r u o f t s r i f s d a e r 0 0 0 01 0 1 0) r e d r o n i 4 , 3 , 2 , 1 , 0 e t y b ( a t a d f o s e t y b e v i f t s r i f s d a e r 0 0 0 00 1 1 0) r e d r o n i 5 , 4 , 3 , 2 , 1 , 0 e t y b ( a t a d f o s e t y b x i s t s r i f s d a e r 0 0 0 01 1 1 0) r e d r o n i 6 , 5 , 4 , 3 , 2 , 1 , 0 e t y b ( a t a d f o s e t y b n e v e s t s r i f s d a e r 0 1 0 00 0 0 02 3 = d e t r o p p u s t n u o c e t y b . x a m 14 ps8410 08/11/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c110e clock solution for 133 mhz celeron/pentium ii/iii processors byte 0 : control register (1 = enable, 0 = disable) byte 1: control register (1 = enable, 0 = disable) byte 2: control register (1 = enable, 0 = disable) pi6c110e conditions at power up all sdram outputs are enabled and active. the sdata and sclk inputs have internal pull-up resistors with values above 100k ohms as well for complete platform flexibility. pi6c110e serial configuration map a) the serial bits will be read by the clock driver in the following order: byte 0 - bits 7, 6, 5, 4, 3, 2, 1, 0 byte 1 - bits 7, 6, 5, 4, 3, 2, 1, 0 byte n - bits 7, 6, 5, 4, 3, 2, 1, 0 b) all unused register bits (reserved and n/a) are designed as don't care. the controller will force all of these bits to a ? 0? level. c) all reserved bits should be programmed to a logic level ? 0.? note: 1. default is for all clocks to be enabled and all reserved bits should be programmed to a logic level ?0.? spread spectrum modulation should power up disabled (byte 0 bit 3 = 0). note: inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. t i b# n i pe m a nn o i t p i r c s e d n i p 7 t i b? ' 0 ' o t e v i r d d e v r e s e r ) e v i t c a n i / e v i t c a ( 6 t i b? ' 0 ' o t e v i r d d e v r e s e r 5 t i b? ' 0 ' o t e v i r d d e v r e s e r 4 t i b? ' 0 ' o t e v i r d d e v r e s e r 3 t i b? m u r t c e p s d a e r p s ) f f o = 0 / n o = 1 ( 2 t i b6 21 b s u 1 t i b5 20 b s u 0 t i b9 42 u p c t i b# n i pe m a nn o i t p i r c s e d n i p 7 t i b6 37 m a r d s ) e v i t c a n i / e v i t c a ( 6 t i b7 36 m a r d s 5 t i b9 35 m a r d s 4 t i b0 44 m a r d s 3 t i b2 43 m a r d s 2 t i b3 42 m a r d s 1 t i b5 41 m a r d s 0 t i b6 40 m a r d s t i b# n i pe m a nn o i t p i r c s e d n i p 7 t i b0 27 i c p ) e v i t c a n i / e v i t c a ( 6 t i b9 16 i c p 5 t i b8 15 i c p 4 t i b6 14 i c p 3 t i b5 13 i c p 2 t i b3 12 i c p 1 t i b2 11 i c p 0 t i b? ' 0 ' o t e v i r d d e v r e s e r byte 3 and byte 4: reserved register (1 = enable, 0 = disable) t i b# n i pe m a nn o i t p i r c s e d n i p 7 t i b? ' 0 ' o t e v i r d d e v r e s e r ) e v i t c a n i / e v i t c a ( 6 t i b? ' 0 ' o t e v i r d d e v r e s e r 5 t i b? ' 0 ' o t e v i r d d e v r e s e r 4 t i b? ' 0 ' o t e v i r d d e v r e s e r 3 t i b? ' 0 ' o t e v i r d d e v r e s e r 2 t i b? ' 0 ' o t e v i r d d e v r e s e r 1 t i b? ' 0 ' o t e v i r d d e v r e s e r 0 t i b? ' 0 ' o t e v i r d d e v r e s e r 15 ps8410 08/11/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c110e clock solution for 133 mhz celeron/pentium ii/iii processors ordering information n / pn o i t p i r c s e d v e 0 1 1 c 6 i pe g a k c a p p o s s n i p - 6 5 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com 56 pin ssop package data 0.25 0.20 .025 bsc 0.635 .008 .008 .016 0-8? 0.20 0.40 .110 2.79 .010 gauge plane .291 .299 x.xx x.xx denotes dimensions in millimeters 7.39 7.59 .396 .416 10.06 10.56 .02 .04 0.51 1.01 .015 .025 0.381 0.635 .720 .730 18.29 18.54 .008 .0135 0.20 0.34 1 56 x 45? nom. max |
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